Some semiconductor devices include a buried channel. A metal-oxide-semiconductor field-effect transistor (MOSFET) that includes a buried channel, for example, can have advantages over a surface-channel MOSFET. For example, a buried-channel MOSFET can have low noise because channel conduction occurs in a layer that is spaced from a dielectric interface.
Buried-channel transistors can include semiconductor layers of a variety materials, such as, silicon, germanium, GaAs, InP, InGaAs, AlGaAs, etc. Devices that include SiGe alloys are presently of particular interest for potential improvements over conventional device performance. Both buried channel layers and surface channel layers can be formed on substrates having a relaxed SiGe layer. These channel layers can provide improved carrier mobility in comparison to convention silicon channel devices.
Buried-channel devices, however, lack good compatibility with traditional MOSFET fabrication methods. Traditional surface-channel MOSFET fabrication typically entails formation of a silicon dioxide (SiO2) gate insulator via thermal oxidation of a silicon surface. For example, a buried silicon channel with a SiGe alloy overlayer having a significant Ge concentration generally will not yield a high-quality thermally grown insulator-semiconductor interface via oxidation of the SiGe overlayer.
A silicon capping layer can be included during fabrication, to support thermal-oxide formation. A silicon cap, however, can cause formation of an undesirable parasitic surface channel in a buried layer device. When the device is “on” (i.e. gate bias above threshold voltage) there can be significant electron confinement in the portion of the surface silicon cap that remains after oxide formation. The parasitic surface channel can decrease effective mobility and degrade noise performance of the MOSFET.
One possible solution to this problem is minimization of the thickness of the silicon cap that remains after thermal oxidation. If the surface electron “well” is very thin, electrons can be excluded from the surface silicon region. This solution can be difficult to implement because of the extremely high degree of precision and repeatability it would demand.
If the surface cap is deposited with too little thickness, the cap can be insufficient for the growth of a good quality SiO2 gate insulator. If oxidation of a silicon cap leaves too much remaining silicon, or no remaining silicon, a parasitic layer or a poor oxide can result. Thus, a flexible process window can be elusive in a production environment.